1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a testing technique for detecting a bit line leak in a semiconductor memory device.
2. Description of the Related Art
In a semiconductor memory device such as a DRAM (Dynamic Static Random Access Memory), if a bit line leak occurs due to, for example, a short-circuit between a bit line and a word line, erroneous data is sometimes read through a read operation as described below. While the semiconductor memory device is in a standby state, an equalizing control signal to an equalizing circuit is activated. The equalizing control circuit connects a pair of bit lines to each other and connects the pair of bit lines to a precharge voltage line. Therefore, a voltage of the pair of bit lines is set to a bit line precharge level. Further, while the semiconductor memory device is in a standby state, a word line control signal to a word line driving circuit is inactivated. The word line driving circuit activates one of a plurality of word lines. Therefore, all the word lines are inactivated at a ground voltage.
When the semiconductor memory device shifts to an active state from the standby state, the equalizing control signal to the equalizing circuit is deactivated. This causes the pair of bit lines to be in a floating state. If, at this time, a short circuit is present, for example, between one of the pair of bit lines and the word line, the voltage of the one of the pair of bit lines drops from the bit line precharge level since all the word lines are set to the ground voltage. Thereafter, the word line control signal to the word line driving circuit is activated, so that a word line corresponding to a memory cell connected to the one of the pair of bit lines is activated to a word line high-level voltage. Consequently, if data “1” is stored in the memory cell connected to the one of the pair of bit lines, the voltage of the one of the pair of bit lines rises owing to electrical charges accumulated in the memory cell.
Then, when a sense amplifier control signal to a sense amplifier for amplifying a voltage difference between the pair of bit lines is activated, the voltage of the bit line connected to the selected memory cell and the voltage of the other one of the pair of bit lines are amplified to a bit line high-level voltage and the ground voltage respectively, and correct data is read by the read operation. If a short circuit between the bit line and the word line is present, the voltage of this bit line is lower than the bit line precharge level, and therefore, it does not become higher than the voltage of the other one of the pair of bit lines even when the data “1” is read from the memory cell. If the sense amplifier control signal is activated in this state, the voltage of the bit line connected to the selected memory cell and the voltage of the other one of the pair of bit lines are amplified to the ground voltage and the bit line high-level voltage respectively, and consequently, erroneous data is read by the read operation. Whether the correct data is read or the erroneous data is read by the read operation is determined by an amount of decrease in the voltage of the bit line when the word line is activated, and thus depends on the magnitude of a leak current of the bit line.
In a semiconductor memory device with a bit line leak, the bit line leak may cause a defect in a circuit after the shipment of the product due to, for example, a decrease in a short circuit resistance value between a bit line and a word line, and it may also cause an operation failure. Therefore, it is necessary to inspect the device on the presence or absence of the bit line leak in a test in manufacturing processes and invalidate a bit line having a leak by taking a measure such as relocating it in a redundant circuit.
Japanese Unexamined Patent Application Publication No. 2001-76498 discloses an technique of detecting a minute bit line leak in a semiconductor memory device having a plurality of blocks (memory cell arrays) and sense amplifiers each shared by two adjacent blocks, in such a manner that, in a test mode, all equalizing control signals are deactivated after a predetermined time passes from the input of a precharge command so as to increase the length of a period during which a pair of bit lines of a selected block are in a floating state, compared with that in a normal mode. Further, Japanese Unexamined Patent Application Publication No. 2002-15598 discloses an art of detecting a minute bit line leak in a semiconductor memory device by making longer a period from the activation of a word line driving circuit to the activation of a sense amplifier in a test mode than that in a normal mode.
In Japanese Unexamined Patent Application Publication No. 2001-76498, only the equalizing control signal corresponding to the selected block operates in the normal mode, but in the test mode, all the equalizing control signals operate. Since a boost voltage is often used as a high-level voltage of the equalizing control signal, in Japanese Unexamined Patent Application Publication No. 2001-76498, it is necessary to devise a special control operation such as increasing a current supply capacity of a power supply circuit or supplying a high voltage via an external terminal in the test mode. Further, in Japanese Unexamined Patent Application Publication No. 2001-76498, since current consumption in the test mode is several times as large as that in the normal mode, it is necessary to thicken an internal power supply line in order to prevent a drop of a power supply voltage due to a wiring resistance. Moreover, in Japanese Unexamined Patent Application Publication No. 2001-76498, it is necessary to add elements in a circuit for generating the equalizing control signal and route new signal lines in a word line driving circuit in order to realize the aforesaid test mode. These measures, if implemented, result in an increase in the chip size of the semiconductor memory device.
Further, in Japanese Unexamined Patent Application Publication No. 2001-76498, in the test mode, the equalizing control signals corresponding to blocks not selected are activated immediately before the word line driving circuit corresponding to the selected block is activated, unlike in the normal mode. Therefore, in the test mode, because of reasons such that the word line is not normally activated due to the voltage drop of the internal power supply line, there is a possibility that erroneous data is read by the read operation. This makes it difficult to decide whether or not the read of the erroneous data, if any, is ascribable to the bit line leak.